In recent years, significantly high data transfer rate is required for data transfer between semiconductor devices (between CPUs and memories for example). To accomplish high data transfer rate, the amplitude of input/output signals is increasingly reduced. If the input/output signals have reduced amplitudes, the desired accuracy of impedances of output buffers becomes severe.
The impedance of the output buffer varies depending on process conditions during the manufacturing. Also, during its actual use, the impedance of the output buffer is affected by variations in ambient temperature and power source voltage. When high impedance accuracy is required for the output buffer, output buffers that can adjust their impedances are utilized (Japanese Patent Application Laid-open Nos. 2002-152032, 2004-32070, 2006-203405, and 2005-159702). The impedance of such an output buffer is adjusted by circuits generally called “calibration circuits”.
As disclosed in Japanese Patent Application Laid-open Nos. 2006-203405, and 2005-159702, the calibration circuit includes a replica buffer with the same configuration as the output buffer. When a calibration operation is performed, with an external resistor connected to a calibration terminal, the voltage of the calibration terminal is compared to the reference voltage and the impedance of the replica buffer is adjusted accordingly. The result of adjustment of the replica buffer is then reflected in the output buffer, and the impedance of the output buffer is thus set to the desired value.
On the other hand, in a semiconductor device such as a DRAM (Dynamic Random Access Memory), the impedance of the output circuit is required to be changeable. To meet this requirement, it is considered suitable to provide plural output buffers having different impedances. However, according to this method, the circuit scale of the total output circuit becomes very large, and the calibration circuit needs to be provided in each output buffer.
In order to solve the above problems, not plural output buffers having different impedances are prepared, but plural unit buffers each having mutually the same configuration are prepared, and the number of unit buffers used in parallel may be changed according to specified impedances. According to this method, when the impedance of one unit buffer is X, the output impedance can be set to X/Y by using Y output buffers in parallel.